The Verilog® Hardware Description Language

Thomas, Donald E.; Moorby, Philip R.

xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

Details

Published by: Springer

Publication Date: 2002-06-30

Format: Hardcover

ISBN-13: 9781402070891

DOI: 10.1007/b116662

Dimensions: 235cm x155cm

Pages: 382