{"product_id":"9783319345345","title":"Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs","description":"\u003ch1\u003eDesign-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs\u003c\/h1\u003e \u003ch2\u003eNoia, Brandon; Chakrabarty, Krishnendu\u003c\/h2\u003e \u003cp\u003eThis book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. \u003cbr\u003e\u003c\/p\u003e \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 2016-08-23\u003c\/p\u003e \u003cp\u003eFormat: Paperback\u003c\/p\u003e \u003cp\u003eISBN-13: 9783319345345\u003c\/p\u003e \u003cp\u003eDOI: 10.1007\/978-3-319-02378-6\u003c\/p\u003e \u003cp\u003eDimensions: 235cm x155cm\u003c\/p\u003e \u003cp\u003ePages: 245\u003c\/p\u003e ","brand":"Springer International Publishing","offers":[{"title":"Default Title","offer_id":47518731534476,"sku":"9783319345345","price":107.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9783319345345.jpg?v=1775967242","url":"https:\/\/fh90cf-fv.myshopify.com\/products\/9783319345345","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}