Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Noia, Brandon; Chakrabarty, Krishnendu

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

Details

Published by: Springer

Publication Date: 2016-08-23

Format: Paperback

ISBN-13: 9783319345345

DOI: 10.1007/978-3-319-02378-6

Dimensions: 235cm x155cm

Pages: 245