Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling

Mandal, Ayan; Khatri, Sunil P.; Mahapatra, Rabi

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

Details

Published by: Springer

Publication Date: 2016-08-23

Format: Paperback

ISBN-13: 9781493948178

DOI: 10.1007/978-1-4614-9405-8

Dimensions: 235cm x155cm

Pages: 143