{"product_id":"9781475779516","title":"Direct Transistor-Level Layout for Digital Blocks","description":"\u003ch1\u003eDirect Transistor-Level Layout for Digital Blocks\u003c\/h1\u003e \u003ch2\u003eGopalakrishnan, Prakash; Rutenbar, Rob A.\u003c\/h2\u003e \u003cp\u003eCell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing\/power are poorly handled in a fixed cell library. \u003cbr\u003e\u003cstrong\u003eDirect Transistor-Level Layout For Digital Blocks\u003c\/strong\u003e proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. \u003cbr\u003eThe essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.\u003cbr\u003e\u003cstrong\u003eDirect Transistor-Level Layout For Digital Blocks\u003c\/strong\u003e is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.\u003c\/p\u003e \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 2013-03-23\u003c\/p\u003e \u003cp\u003eFormat: Paperback\u003c\/p\u003e \u003cp\u003eISBN-13: 9781475779516\u003c\/p\u003e \u003cp\u003eDOI: 10.1007\/b117054\u003c\/p\u003e \u003cp\u003eDimensions: 235cm x155cm\u003c\/p\u003e \u003cp\u003ePages: 125\u003c\/p\u003e ","brand":"Springer US","offers":[{"title":"Default Title","offer_id":46266462077068,"sku":"9781475779516","price":98.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9781475779516.jpg?v=1770821893","url":"https:\/\/fh90cf-fv.myshopify.com\/products\/9781475779516","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}