Lecture Notes in Electrical Engineering

Murali, Srinivasan

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.

Details

Published by: Springer

Publication Date: 2009-04-21

Format: Hardcover

ISBN-13: 9781402097560

DOI: 10.1007/978-1-4020-9757-7

Dimensions: 235cm x155cm

Pages: 198