{"product_id":"9780792398295","title":"Computer-Aided Design Techniques for Low Power Sequential Logic Circuits","description":"\u003ch1\u003eComputer-Aided Design Techniques for Low Power Sequential Logic Circuits\u003c\/h1\u003e \u003ch2\u003eMonteiro, José; Devadas, Srinivas\u003c\/h2\u003e \u003cp\u003eRapid increases in chip complexity, increasingly faster clocks,  and the proliferation of portable devices have combined to make power  dissipation an important design parameter. The power consumption of a  digital system determines its heat dissipation as well as battery  life. For some systems, power has become the most critical design  constraint. \u003cbr\u003e  \u003cem\u003eComputer-Aided Design Techniques for Low Power Sequential Logic\u003c\/em\u003e  \u003cem\u003eCircuits\u003c\/em\u003e presents a methodology for low power design. The  authors first present a survey of techniques for estimating the  average power dissipation of a logic circuit. At the logic level,  power dissipation is directly related to average switching activity. A  symbolic simulation method that accurately computes the average  switching activity in logic circuits is then described. This method is  extended to handle sequential logic circuits by modeling correlation  in time and by calculating the probabilities of present state lines.  \u003cbr\u003e  \u003cem\u003eComputer-Aided Design Techniques for Low Power Sequential Logic\u003c\/em\u003e  \u003cem\u003eCircuits\u003c\/em\u003e then presents a survey of methods to optimize logic  circuits for low power dissipation which target reduced switching  activity. A method to retime a sequential logic circuit where  registers are repositioned such that the overall glitching in the  circuit is minimized is also described. The authors then detail a  powerful optimization method that is based on selectively precomputing  the output logic values of a circuit one clock cycle before they are  required, and using the precomputed value to reduce internal switching  activity in the succeeding clock cycle. \u003cbr\u003e  Presented next is a survey of methods that reduce switching activity  in circuits described at the register-transfer and behavioral levels.  Also described is a scheduling algorithm that reduces power  dissipation by maximising the inactivity period of the modules in a  given circuit. \u003cbr\u003e  \u003cem\u003eComputer-Aided Design Techniques for Low Power Sequential Logic\u003c\/em\u003e  \u003cem\u003eCircuits\u003c\/em\u003e concludes with a summary and directions for future  research.\u003c\/p\u003e \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 1996-11-30\u003c\/p\u003e \u003cp\u003eFormat: Hardcover\u003c\/p\u003e \u003cp\u003eISBN-13: 9780792398295\u003c\/p\u003e \u003cp\u003eDOI: 10.1007\/978-1-4615-6319-8\u003c\/p\u003e \u003cp\u003eDimensions: 235.0cm x155.0cm\u003c\/p\u003e \u003cp\u003ePages: 181.0\u003c\/p\u003e ","brand":"Springer US","offers":[{"title":"Default Title","offer_id":45578418061452,"sku":"9780792398295","price":152.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9780792398295.jpg?v=1767146607","url":"https:\/\/fh90cf-fv.myshopify.com\/products\/9780792398295","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}