{"product_id":"9780792397229","title":"Software Synthesis from Dataflow Graphs","description":"\u003ch1\u003eSoftware Synthesis from Dataflow Graphs\u003c\/h1\u003e \u003ch2\u003eBhattacharyya, Shuvra S.; Murthy, Praveen K.; Lee, Edward A.\u003c\/h2\u003e \u003cp\u003e\u003cem\u003eSoftware Synthesis from Dataflow Graphs\u003c\/em\u003e addresses the  problem of generating efficient software implementations from  applications specified as synchronous dataflow graphs for programmable  digital signal processors (DSPs) used in embedded real- time systems.  The advent of high-speed graphics workstations has made feasible the  use of graphical block diagram programming environments by designers  of signal processing systems. A particular subset of dataflow, called  Synchronous Dataflow (SDF), has proven efficient for representing a  wide class of unirate and multirate signal processing algorithms, and  has been used as the basis for numerous DSP block diagram-based  programming environments such as the Signal Processing Workstation  from Cadence Design Systems, Inc., COSSAP from Synopsys\u003csup\u003e®\u003c\/sup\u003e  (both commercial tools), and the Ptolemy environment from the  University of California at Berkeley. \u003cbr\u003e  A key property of the SDF model is that static schedules can be  determined at compile time. This removes the overhead of dynamic  scheduling and is thus useful for real-time DSP programs where  throughput requirements are often severe. Another constraint that  programmable DSPs for embedded systems have is the limited amount of  on-chip memory. Off-chip memory is not only expensive but is also  slower and increases the power consumption of the system; hence, it is  imperative that programs fit in the on-chip memory whenever possible.  \u003cbr\u003e  \u003cem\u003eSoftware Synthesis from Dataflow Graphs\u003c\/em\u003e reviews the  state-of-the-art in constructing static, memory-optimal schedules for  programs expressed as SDF graphs. Code size reduction is obtained by  the careful organization of loops in the target code. Data buffering  is optimized by constructing the loop hierarchy in provably optimal  ways for many classes of SDF graphs. The central result is a  uniprocessor scheduling framework that provably synthesizes the most  compact looping structures, called singleappearance schedules, for a  certain class of SDF graphs. In addition, algorithms and heuristics  are presented that generate single appearance schedules optimized for  data buffering usage. Numerous practical examples and extensive  experimental data are provided to illustrate the efficacy of these  techniques.\u003c\/p\u003e \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 1996-05-31\u003c\/p\u003e \u003cp\u003eFormat: Hardcover\u003c\/p\u003e \u003cp\u003eISBN-13: 9780792397229\u003c\/p\u003e \u003cp\u003eDOI: 10.1007\/978-1-4613-1389-2\u003c\/p\u003e \u003cp\u003eDimensions: 234.0cm x156.0cm\u003c\/p\u003e \u003cp\u003ePages: 190.0\u003c\/p\u003e ","brand":"Springer US","offers":[{"title":"Default Title","offer_id":44697969852556,"sku":"9780792397229","price":98.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9780792397229.jpg?v=1767145445","url":"https:\/\/fh90cf-fv.myshopify.com\/products\/9780792397229","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}