{"product_id":"9780792375456","title":"Stream Processor Architecture","description":"\u003ch1\u003eStream Processor Architecture\u003c\/h1\u003e \u003ch2\u003eRixner, Scott\u003c\/h2\u003e \u003cp\u003eMedia processing applications, such as three-dimensional  graphics, video compression, and image processing, currently demand  10-100 billion operations per second of sustained computation.  Fortunately, hundreds of arithmetic units can easily fit on a modestly  sized 1cm2 chip in modern VLSI.  The challenge is to provide these  arithmetic units with enough data to enable them to meet the  computation demands of media processing applications.  Conventional  storage hierarchies, which frequently include caches, are unable to  bridge the data bandwidth gap between modern DRAM and tens to hundreds  of arithmetic units.  A data bandwidth hierarchy, however, can bridge  this gap by scaling the provided bandwidth across the levels of the  storage hierarchy. \u003cbr\u003e  The stream programming model enables media processing applications to  exploit a data bandwidth hierarchy effectively.  Media processing  applications can naturally be expressed as a sequence of computation  kernels that operate on data streams.  This programming model exposes  the locality and concurrency inherent in these applications and  enables them to be mapped efficiently to the data bandwidth hierarchy.  Stream programs are able to utilize inexperience local data bandwidth  when possible and consume expensive global data bandwidth only when  necessary. \u003cbr\u003e  \u003cem\u003eStream Processor Architecture\u003c\/em\u003e presents the architecture of the  Imagine streaming media processor, which delivers a peak performance  of 20 billion floating-point operations per second.  Imagine  efficiently supports 48 arithmetic units with a three-tiered data  bandwidth hierarchy.  At the base of the hierarchy, the streaming  memory system employs memory access scheduling to maximize the  sustained bandwidth of external DRAM.  At the center of the hierarchy,  the global stream register file enables streams of data to be  recirculated directly from one computation kernel to the next without  returning data to memory.  Finally, local distributed register files  that directly feed the arithmetic units enable temporary data to be  stored locally so that it does not need to consume costly global  register bandwidth.  The bandwidth hierarchy enables Imagine to  achieve up to 96\u0026amp;percnt; of the performance of a stream processor with  infinite bandwidth from memory and the global register file.\u003c\/p\u003e \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 2001-10-31\u003c\/p\u003e \u003cp\u003eFormat: Hardcover\u003c\/p\u003e \u003cp\u003eISBN-13: 9780792375456\u003c\/p\u003e \u003cp\u003eDOI: \u003c\/p\u003e \u003cp\u003eDimensions: 235.0cm x155.0cm\u003c\/p\u003e \u003cp\u003ePages: 120.0\u003c\/p\u003e ","brand":"Springer US","offers":[{"title":"Default Title","offer_id":45578393190540,"sku":"9780792375456","price":98.1,"currency_code":"USD","in_stock":true}],"url":"https:\/\/fh90cf-fv.myshopify.com\/products\/9780792375456","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}