The Verilog® Hardware Description Language

Thomas, Donald; Moorby, Philip

XV From the Old to the New xvii Acknowledgments xx| Verilog A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits 11 Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Procedural Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

Details

Published by: Springer

Publication Date: 2008-10-08

Format: Paperback

ISBN-13: 9780387849300

DOI: 10.1007/978-0-387-85344-4

Dimensions: 235cm x155cm

Pages: 386